Developping JavaRock is over, and the project continues in Synthesijer.
Like JavaRock, Synthesijer also aims to develop a compiler from Java to VHDL, which enables hardware design by Java. In addition, Synthesijer generates Verilog HDL and aims to implement advanced features such as optimization, graphical tools, and so on.


About JavaRock

Quick Start

Download JavaRock

Download JavaRock from here.

Writing 1st Program

This is a sample program to compile with JavaRock.

public class Test extends Thread{
  private boolean flag;
  private int count;

  public boolean isFlag(){
    return flag;

  public void run(){
      if(count > 1000000){
	count = 0;
	flag = !flag;
You can compile the sample code with JavaRock as following:
java -cp javarock_r155.jar
After compilation, "test.vhd" should be generated.

Writing Top Module

You should write a top module to instantiate the generated module. The entity of the generated HDL module is the following code.

entity test is
  port (
    notify_method_busy : OUT std_logic;
    run_method_busy : OUT std_logic;
    output_port_isFlag : OUT std_logic;
    isFlag_method_busy : OUT std_logic;
    notify_method_request : IN std_logic;
    clk : IN std_logic;
    reset : IN std_logic;
    isFlag_method_request : IN std_logic;
    run_method_request : IN std_logic
end test;
Unfortunately, top module cannot be written by pure Java program. You should use "JavaRock HDL", which supports some annotations in order to write HDL by Java. The following code is a top module code for the above example.
import net.wasamon.javarock.rt.*;

public class Top{
  final Test test = new Test();
  boolean flag;

  public boolean output(){
    return flag;

  public void main(){
      flag = test.isFlag();
To compile the example programs by the following command.
java -cp javarock_r155.jar
You get two files "test.vhd" and "top.vhd" after the compilation. The generated files are synthesizable by existing tools, such as Xilinx ISE and QuartusII.

Writing Pin Assignment Configuration File

Generally, you have to write a configuration file for P&R tools (ex. "ucf" or "qpf") to realize required mapping for your target board.
The generated entity for the above example top module is

entity top is
  port (
    notify_method_busy : OUT std_logic;
    output_port_output : OUT std_logic;
    notify_method_request : IN std_logic;
    clk : IN std_logic;
    reset : IN std_logic
end top;
In this file, "output_port_output" corresponds to the return value of "output" function. When you use Avnet Spartan-6 LX9 MicroBoard, the UCF file is as follow.
NET reset              LOC = V4  | IOSTANDARD = LVCMOS33 | PULLDOWN;    # "USER_RESET"
NET clk                LOC = C10 | IOSTANDARD = LVCMOS33;               # "CLOCK_Y3"
NET output_port_output LOC = P4  | IOSTANDARD = LVCMOS18;               # "GPIO_LED1"

Synthesize, Place & Route, and Download

As usual.


You can see some samples that are available on samples_r155.tar.gz. This archive includes such as
blinking led
printing characters onto SC1602 (famous charactor display)
echo via serial port
VGA test program
And two sample environments are included. You can compile each sample by executing "" in each folder.
the test environment for Virtex-6 FPGA ML605 Evaluation Kit
the test environment for Avnet Spartan-6 LX9 MicroBoard


Copyright (C) 2011 Takefumi MIYOSHI
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

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